ENTITY rf2_mid_mem_r0 IS
PORT (
  dinx	 : in  BIT;
  write  : in  BIT;
  reada  : in  BIT;
  readb  : in  BIT;
  busa   : out MUX_BIT BUS;
  busb   : out MUX_BIT BUS;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END rf2_mid_mem_r0;

ARCHITECTURE VBE OF rf2_mid_mem_r0 IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf2_mid_mem_r0"
  SEVERITY WARNING;

  label1 : BLOCK (reada = '1')
  BEGIN
    busa <= GUARDED '0';
  END BLOCK label1;

  label2 : BLOCK (readb = '1')
  BEGIN
    busb <= GUARDED '0';
  END BLOCK label2;


END;
