ENTITY rom_dec_line67 IS
PORT (
  nck6    : in  BIT;
  nck7    : in  BIT;
  sel6    : in  BIT;
  sel7    : in  BIT;
  col     : in  BIT;
  line6   : out  BIT;
  line7   : out  BIT;
  vdd	  : in  BIT;
  vss	  : in  BIT
);
END rom_dec_line67;

ARCHITECTURE VBE OF rom_dec_line67 IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rom_dec_line67"
  SEVERITY WARNING;

  line6 <= nck6 and sel6 and col;
  line7 <= nck7 and sel7 and col;

END;
