-- VHDL data flow description generated from `pvddick_sp`
--		date : Thu Feb 23 17:12:35 1995


-- Entity Declaration

ENTITY pvddick_sp IS
  GENERIC (
    CONSTANT area : NATURAL := 86000;	-- area
    CONSTANT cin_ck : NATURAL := 127;	-- cin_ck
    CONSTANT tpll_ck : NATURAL := 1235;	-- tpll_ck
    CONSTANT rdown_ck : NATURAL := 253;	-- rdown_ck
    CONSTANT tphh_ck : NATURAL := 1109;	-- tphh_ck
    CONSTANT rup_ck : NATURAL := 311	-- rup_ck
  );
  PORT (
  cko : out WOR_BIT BUS;	-- cko
  ck : in BIT;	-- ck
  vdde : in BIT;	-- vdde
  vddi : in BIT;	-- vddi
  vsse : in BIT;	-- vsse
  vssi : in BIT	-- vssi
  );
END pvddick_sp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF pvddick_sp IS

BEGIN
  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
    REPORT "power supply is missing on pvddick_sp"
    SEVERITY WARNING;

	label0 : BLOCK ('1' = '1')
	BEGIN
	cko <= GUARDED ck;
	END BLOCK label0;
END;
