ENTITY rf_mid_buf_2 IS
PORT (
  selr   : in  BIT;
  selw   : in  BIT;
  nck    : in  BIT;
  read	 : out BIT;
  write  : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END rf_mid_buf_2;

ARCHITECTURE VBE OF rf_mid_buf_2 IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf_mid_buf_2"
  SEVERITY WARNING;

  read <= selr;
  write <= selw and nck;

END;
