ENTITY dp_ts_x4_buf IS
PORT (
  en	 : in  BIT;
  enx	 : out BIT;
  nenx	 : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END dp_ts_x4_buf;

ARCHITECTURE vbe OF dp_ts_x4_buf IS

BEGIN
  ASSERT (vdd and not vss)
  REPORT "power supply is missing on dp_ts_x4_buf"
  SEVERITY WARNING;

  enx <= en;
  nenx <= not en;

END;
