-- VHDL data flow description generated from `corner_sp`
--		date : Thu Feb 23 17:06:23 1995


-- Entity Declaration

ENTITY corner_sp IS
  PORT (
  ck : in BIT;	-- ck
  vdde : in BIT;	-- vdde
  vddi : in BIT;	-- vddi
  vsse : in BIT;	-- vsse
  vssi : in BIT	-- vssi
  );
END corner_sp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF corner_sp IS

BEGIN
  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
    REPORT "power supply is missing on corner_sp"
    SEVERITY WARNING;

END;
